Regviz

NXP Semiconductors /MIMXRT1011 /LPI2C1 /MCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/MIMXRT1011/LPI2C1/MCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MEN_0)MEN 0 (RST_0)RST 0 (DOZEN_0)DOZEN 0 (DBGEN_0)DBGEN 0 (RTF_0)RTF 0 (RRF_0)RRF

RRF=RRF_0, RST=RST_0, DBGEN=DBGEN_0, DOZEN=DOZEN_0, MEN=MEN_0, RTF=RTF_0

Description

Master Control Register

Fields

MEN

Master Enable

0 (MEN_0): Master logic is disabled

1 (MEN_1): Master logic is enabled
RST

Software Reset

0 (RST_0): Master logic is not reset

1 (RST_1): Master logic is reset
DOZEN

Doze mode enable

0 (DOZEN_0): Master is enabled in Doze mode

1 (DOZEN_1): Master is disabled in Doze mode
DBGEN

Debug Enable

0 (DBGEN_0): Master is disabled in debug mode

1 (DBGEN_1): Master is enabled in debug mode
RTF

Reset Transmit FIFO

0 (RTF_0): No effect

1 (RTF_1): Transmit FIFO is reset
RRF

Reset Receive FIFO

0 (RRF_0): No effect

1 (RRF_1): Receive FIFO is reset

Links

()

Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data